MT8971B/72B

9-123

Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode

Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode

† Timing is over recommended temperature & power supply voltage ranges.

* Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing.

Figure 18 - RCK, TCK & CLD Timing For MOD Mode

Characteristics

Sym

80 kbit/s

160 kbit/s

Units

Test

Conditions

Min

Typ*

Max Min

Typ*

Max

1TCK/RCK Clock Period

12.5

6.25

µs

2 TCK/RCK Clock Width

6.25

3.125

µs

3 TCK/RCK Clock Transition Time

20

20

ns

4CLD to TCK Setup Time

3.125

1.56

µs

5CLD to TCK Hold Time

3.125

1.56

µs

6CLD Width Low

6.05

2.925

µs

7CLD Period

µs

C4

F0

2.0V

0.8V

2.0V

0.8V

C4

OSC1

2.0V

0.8V

3.0V

2.0V

Φ

RCK

TCK

CLD

2.4V

0.4V

2.4V

0.4V

2.4V

0.4V

Note 1: TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the

and may be skewed with respect to TCK due to end-to-end delay.

Note 2: At the slave end TCK is phase locked to RCK.

The rising edge of TCK will lead the rising edge of RCK by approximately 90