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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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PDSP1601 Scheda tecnica(PDF) 14 Page - Mitel Networks Corporation |
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PDSP1601 Scheda tecnica(HTML) 14 Page - Mitel Networks Corporation |
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14 / 18 page  PDSP1601 MC 14 Min. 2.4 2.5 Vdd -1 -10 -50 12 PDSP1601 Value Typ. 5 ELECTRICAL CHARACTERISTICS Operating Conditions (unless otherwise stated) T AMB (Military) = -55°C to +125°C, V CC = 5.0V±10%, Ground = 0V Characteristic * Output high voltage * Output low voltage * Input high voltage * Input low voltage * Input leakage current * Vcc current * Output leakage current † Output S/C current † Input capacitance Max. 0.4 0.8 0.5 +10 60 +50 80 Units V V V V V V µA mA µA mA pF Symbol V OH V OL V IH V IL V IH V IL I IL I CC I OZ I SC C IN Static Characteristics Min. 5 5 5 30 40 40 40 5 200 100 40 40 Max. 40 100 100 0 0 0 3 0 3 100 40 40 40 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns sn Switching Characteristics Characteristics Value Conditions I OH = 8mA I OL = -8mA CLOCK, OE CLOCK, OE GND < V IN < VCC T amb = -40°C to +85°C GND < V OUT < VCC V CC = Max Sub group 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 2 x LSTTL + 20pF 1 x LSTTL + 5pF 1 x LSTTL + 5pF Input mode Input mode 20pF load, SV O P mode 2 x LSTTL + 20pF 2 x LSTTL + 20pF 2 x LSTTL + 20pF 2 x LSTTL + 20pF 9, 10, 11 Units Sub group Conditions CLK rising edge to C-PORT CLK rising edge to CO CLK rising edge to BFP Setup CEA or CEB to CLK rising edge Hold CEA or CEB to CLK rising edge Setup A or B port inputs to CLK rising edge Hold A or B port inputs to CLK rising edge Setup MSA0-1, MSB, MSS, MSC, RA2-0, RS0-2, IA0-4, IS0-3, to CLK rising edge Hold RS0-2, IA0-4 to CLK rising edge Hold IS0-3 to CLK rising edge Hold MSA0-1, MSB, MSS, MSC, RA0-2 to CLK rising edge Setup SV to CLK rising edge Hold SV to CLK rising edge CLK rising edge to SV OE C-PORT Z OE C-PORT Z OE C-PORT Z OE C-PORT Z Clock period (ALU & Barrel Shifter, serial mode) Clock period (ALU & Barrel Shifter, parallel mode) Clock high time Clock low time † † † † † † † † † † † † † † † † † † † * † † All parameter marked * are tested during production. Parameters marked † are guaranteed by design and characterisation |
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