VP306 datasheet(49/85 Pages) MITEL

49 / 85 page

DRAFT - PRELIMINARY DATA

VP305/6

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

2.10.4.

VI_BER_PER: Viterbi bit error rate based synchronisation period register.

Parallel mode -

Bank 5. Address 6.

Type Read / Write.

Serial mode - Address 46.

7654

3210

VBPER[7:0] - Viterbi bit error rate based synchronisation period

VBPER[7:0]

Viterbi bit error rate based synchronisation period.

The actual period = 256 x VBPER[7:0] data bits.

2.10.5.

VI_BER_LIM: Viterbi bit error rate based synchronisation limit register.

Parallel mode -

Bank 5. Address 7.

Type Read / Write.

Serial mode - Address 47.

76543210

VBLIM[7:0] - Viterbi bit error rate based synchronisation limit

VBLIM[7:0]

Viterbi bit error rate based synchronisation limit.

The actual limit = 128 x VBLIM[7:0] + 32 data bits.

The Viterbi bit error rate threshold is the ratio of the register values:

Threshold = VI_BER_LIM / VI_BER_PER

The following table shows recommended threshold values for the various Viterbi code rates. If the

Viterbi bit error rate threshold is set too low, the Viterbi circuit will lock up on incorrect data. But

conversely, if the threshold is set too high, the Viterbi circuit will have difficulty in llocking up. A

false lock may be exited by toggling F_LOCK (bit 6 of VIT_MODE register, see page 47).

Coding rate

min.

max.

1/2

0.090

0.120

2/3

0.055

0.070

3/4

0.035

0.050

5/6

0.020

0.035

7/8

0.010

0.025

Table 9. Viterbi bit error rate threshold. .

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