EM44DM0888LBA_15 datasheet(8/29 Pages) EOREX

8 / 29 page

EM44DM0888LBA

Feb. 2012

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Recommended DC Operating Conditions

(VDD=1.8V±0.1V)

Symbol

Parameter

Test Conditions

-187(1066)

-25(800)

Units

Max

IDD1

Operating Current

(Note 1)

IOUT = 0mA

BL = 4, CL = CL(IDD), AL = 0

tCK = tCK(IDD), tRC = tRC (IDD)

tRAS = tRASmin(IDD), tRCD = tRCD(IDD)

CKE=HIGH

CS=HIGH between valid commands

Address bus inputs are SWITCHING

Data pattern is same as IDD4W

102

IDD2P

Precharge Standby Current

in Power Down Mode

All banks idle

tCK = tCK(IDD), CKE is LOW

Other control and address bus inputs are

STABLE

Data bus inputs are FLOATING

IDD2N

Precharge Standby Current

in NON-power down mode

All banks idle

tCK = tCK(IDD), CKE is HIGH, CS is HIGH

Other control and address bus inputs are

SWITCHING

Data bus inputs are SWITCHING

IDD3P

Active Standby Current in

Power Down Mode (A12=0)

All banks open

tCK = tCK(IDD), CKE is LOW

Other control and address bus inputs are

STABLE

Data bus inputs are FLOATING

IDD3P

Active Standby Current in

Power Down Mode (A12=1)

IDD3N

Active Standby Current

in Non-power Down Mode

All banks open

tCK = tCK(IDD), tRAS = tRASmax(IDD)

tRP = tRP(IDD), CKE is HIGH

CS is HIGH between valid commands

Other control and address bus inputs are

SWITCHING

Data bus inputs are SWITCHING

IDD4W

Operating

Current

(Burst

Mode)

(Note 2)

All banks open, Continuous burst writes

BL = 4, CL = CL(IDD), AL = 0

tCK = tCK(IDD), tRAS = tRASmax(IDD)

tRP = tRP(IDD), CKE is HIGH

CS is HIGH between valid commands

Address bus inputs are SWITCHING

Data bus inputs are SWITCHING

144

120

IDD4R

144

120

IDD5

Refresh Current

(Note 3)

tCK = tCK(IDD)

Refresh command at every tRFC(IDD) interval

CKE is HIGH, CS is HIGH between valid

commands

Other control and address bus inputs are

SWITCHING

Data bus inputs are SWITCHING

210

175

IDD6

Self Refresh Current

CK and CK at 0 V, CKE 0.2 V

Other control and address bus inputs are

FLOATING, Data bus inputs are FLOATING

IDD7

Operating Current

All bank interleaving reads

IOUT = 0mA, BL = 4, CL = CL(IDD)

AL = tRCD(IDD) - 1 x tCK(IDD)

tCK = tCK(IDD), tRC = tRC(IDD)

tRRD = tRRD(IDD), tFAW = tFAW(IDD)

tRCD = 1 x tCK(IDD), CKE is HIGH

CS is HIGH between valid commands

Address bus inputs are STABLE during

DESELECTs

Data pattern is same as IDD4R

300

250

*All voltages referenced to VSS.

Note 1: IDD1 depends on output loading and cycle rates. (CL=CLmin, AL=0)

Note 2: IDD4 depends on output loading and cycle rates. Input signals SWITCHING

Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics.

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