MN101LR05D datasheet(2/34 Pages) PANASONIC

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MN101LR05D/04D/03D/02D

8-bit Single-chip Microcontroller

Publication date: October 2014

PubNo. 21705-019E

1.2

Hardware Features

 Features

In this document, the divided clock and the frequency of it are described as follows:

Divided clock:Clock name/n (n: division ratio)

Frequency:

fClock name

•CPU Core

- AM13L core

- LOAD-STORE architecture (3- or 4-stage Pipeline)

• Machine Cycle and Operating Voltage

- High-Speed mode

100 ns / 10 MHz (Max) (VDD30: 1.8 V to 3.6 V)

1.0

s / 1 MHz (Max) (V

DD30: 1.3 V to 3.6 V)

- Low-Speed Mode

s / 40 kHz (Max)

(VDD30: 1.1 V to 3.6 V)

• Operating Mode

- NORMAL mode (High-Speed mode)

- SLOW mode

(Low-Speed mode)

- HALT mode

(High-Speed/Low-Speed mode)

- STOP mode

• Embedded Memory

- ROM (ReRAM): 64 KB (Programmable area and Data area vary depending on the ROM name.

For details, see Table:1.1.1.)

- RAM:

4 KB

• ReRAM Specification

- Program voltage (VDD30): 1.8 V to 3.6 V

- Program cycles:

1000 times (Program area), 100000 times (Data area)

- Data is rewritable in bytes without data erase.

• Clock Oscillator (4 circuits)

- External Low-Speed Oscillation (SOSCCLK): 32.768 kHz (crystal or ceramic)

- External High-Speed Oscillation (HOSCCLK): up to 10 MHz (crystal or ceramic)

- Internal Low-Speed Oscillation (SRCCLK):

40 kHz ± 20 % (VDD30: 1.1 V to 3.6 V)

- Internal High-Speed Oscillation (HRCCLK):

10/8 MHz ± 3 % (VDD30: 1.8 V to 3.6 V)

1 MHz ± 10 % (VDD30: 1.3 V to 3.6 V)

* MN101LR02D does not have external high-speed oscillation (HOSCCLK).

• Internal Operating Clock

- System Clock (SYSCLK): 10 MHz (Max)

SYSCLK is generated by dividing HCLK or SCLK, and the division ratio is 1, 2, 4, 8, 16 or 32.

HCLK: HOSCCLK or HRCCLK

SCLK: SOSCCLK or SRCCLK

* MN101LR02D cannot be selected HOSCCLK.

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