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Z86C08 Scheda tecnica(PDF) 21 Page - Zilog, Inc. |
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Z86C08 Scheda tecnica(HTML) 21 Page - Zilog, Inc. |
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21 / 34 page ![]() Z86C04/C08 Zilog CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers DS97DZ80502 P R E L I M I N A R Y 21 1 FUNCTIONAL DESCRIPTION RESET. Upon power-up the Power-On Reset circuit waits for T POR ms, plus 18 clock cycles, and then starts program execution at address%000C (Hex) (Figure 10). The device control registers’ reset value is shown in Table 2. Figure 9. Internal Reset Configuration Table 1. Z86C04/C08 & C05/C07 Control Registers Reset Condition Addr. Reg. D7 D6 D5 D4 D3 D2 D1 D0 Comments 03H (3)* Port 3 U UUUU U U U 02H (2)* Port 2 U UUUU U U U 00H (0)* Port 0 U UUUU U U U FFH(255) SPL 0 0000 0 0 0 FFH (254) GPR 0 0000 0 0 0 FDH (253) RP 0 0000 0 0 0 FCH (252) FLAGS U UUUU U U U FBH (251) IMR 0 UUUU U U U FAH (250) IRQ U U 0 0 0 0 0 0 IRQ3 is used for positive edge detection F9H (249) IPR U UUUU U U U F8H (248)* P01M U U U 0 U U 0 1 F7H (247)* P3M U UUUU U 0 0 F6H (246)* P2M 1 1111 1 1 1 Inputs after reset F5H (245) PRE0 U UUUU U U 0 F4H (244) T0 U UUUU U U U F3H (243) PRE1 U UUUU U 0 0 F2H (242) T1 U UUUU U U U F1H (241) TMR 0 0000 0 0 0 Note: *Registers are not reset after a STOP-Mode Recovery using P27 pin. A subsequent reset will cause these control registers to be re-configured as shown in Table 2 and the user must avoid bus contention on the port pins or it may affect device reliability. POR (Cold Start) P27 (Stop Mode) Delay Line TPOR ms 18 CLK Reset Filter Chip Reset XTAL OSC INT OSC |
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