AS3695C datasheet(13/40 Pages) AMSCO

13 / 40 page

AS3695C

austriamicrosystems

www.austriamicrosystems.com

Rev 1.11 / 2010-12-08

12 - 39

External Clock signal. This is usually the HSYNC signal of the TV.

Internal clock signal that is synchronized to the external VSYNC signal by means of a PLL

The VSYNC input can be used as reference clock for the PLL and also as reset signal for all PWM-

generators.

4.2.2 PWM-counter

Each PWM-generator is build with a 12bit counter and digital comparators. The counter is counting up

with tclk until the value stored in “PWMper” is reached. This resets the counter and starts the next period.

While the counter value is below “PWMxHT” the PWM-singal is “1”, the rest of the period the PWM-

signal is “0”. The output of each PWM-generator can also be inverted by means of the “PWMrev”.

4.2.3 SPI data update, UPDATEmode bit

The PWM-settings that are programmed via the SPI-Interface take effect depending on the status of the

“UPDATEmode”-bit.

If UPDATEmode =1 new data from the serial interface are stored at the next rising edge of VSYNC

If UPDATEmode =0 new data from the serial interface are stored immediately after xCS goes high and

will take effect after current PWM cylce is finished. In this mode the values in the PWMxdel registers are

ignored. There will be no Delay on the PWM signals.

Delay

Counter

Compare

Reset

res

clk

Compare

PWM

Reset

PWMper

PWMxdel

PWMrev

PWMxHT

PWMxDEL

PWMper

VSYNC

PWMx

*tclk

clk

PWM-parameter update at third rising edge

VSYNC

clk

SCLK

SDI

xCS

PWM-parameter update. Takes effect after current PWM cycle has finished

If UPDATEmode = 0

If UPDATEmode = 1

No PW M update allowed

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