Si516

10

Rev. 1.0

Table 8. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Phase Jitter

(RMS)

φJ

1.875 MHz to 20 MHz integration

bandwidth2 (brickwall)

—0.25

0.35

ps

12 kHz to 20 MHz integration band-

width2 (brickwall)

—0.8

1.1

ps

Phase Noise,

156.25 MHz

φN100 Hz

—

–71

—

dBc/Hz

1kHz

—

–93

—

dBc/Hz

10 kHz

—

–113

—

dBc/Hz

100 kHz

—

–123

—

dBc/Hz

1 MHz

—

–136

—

dBc/Hz

Spurious

SPR

LVPECL output, 156.25 MHz,

offset > 10 kHz

—–75

—

dBc

Notes:

1.

Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5 MHz.

2.

Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.

Table 9. Environmental Compliance and Package Information

Parameter

Conditions/Test Method

Mechanical Shock

MIL-STD-883, Method 2002

Mechanical Vibration

MIL-STD-883, Method 2007

Solderability

MIL-STD-883, Method 2003

Gross and Fine Leak

MIL-STD-883, Method 1014

Resistance to Solder Heat

MIL-STD-883, Method 2036

Moisture Sensitivity Level

MSL 1

Contact Pads

Gold over Nickel