DLPC910 datasheet(16/50 Pages) TI1

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LVDS Interface

DCLKIN(A,B,C,D),DVALID(A,B,C,D),DIN(A,B,C,D)(15:0)

DLPC910

DOUT(A,B,C,D)

DCLKOUT (A,B,C,D)

SCTRL(A,B,C,D)

RESET_ADDR(3:0)

RESET_MODE(1:0)

RESET_SEL(1:0)

RESET_STRB

RESET_OEZ

RESET_IRQZ

SCP BUS(3:0)

OSC

50 MHz

CTRL_RSTZ

JTAG(3:0)

DLPR910

PGM(4:0)

I2C

Row and Block Signals

ROWMD(1:0),ROWAD(10:0),BLKMD(1:0),BLKAD(3:0),RST2BLKZ

Control Signals

COMP_DATA,NS_FLIP,WDT_ENBLZ,PWR_FLOAT

Status Signals

RST_ACTIVE,INIT_ACTIVE,ECP2_FINISHED

RESETZ

VLED0

VLED1

PWR

GND

CLKIN_R

DLPC910

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

www.ti.com

7 Detailed Description

7.1 Overview

The DLPC910 digital controller provides a reliable high speed data pipe to the DMD, where the digital input on

the LVDS interface is configured for the required timing requirements of the DMD. The DMD reflects light by

using 1-bit binary encoded patterns, where each mirror is a pixel-to-mirror mapping of the pattern.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Input LVDS Interface

The data input interface consists of four input data buses: DDC_DIN_A, DDC_DIN_B, DDC_DIN_C, and

DDC_DIN_D. Each bus contains 16 differential pairs which are synchronous to the rising and falling edges of its

associated DDC_DCLK signal.

7.3.2 Data Clock

The data clock interface consists of four differential pairs: DDC_DCLK_A, DDC_DCLK_B, DDC_DCLK_C, and

DDC_DCLK_D. Each must operate continuously. All signals associated with the data clock should be

synchronous to these signals. For example, DDC_DIN_A and DVALID_A should be synchronous to the rising

edge of DDC_DCLK_A. This clock should be valid prior to releasing CTRL_RSTZ. DDC_DCLK is a DDR clock

with data loaded on both rising and falling edges of DDC_DCLK. The jitter on this clock is specified in Timing

Requirements.

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