TS7001

Page 8

TS7001 Rev. 1.0

PIN FUNCTIONS

PIN

LABEL

DESCRIPTION

1

CS

Chip Select: As an active low logic input signal, the CS input provides the dual function of

initiating TS7001 conversions as well as framing the serial data transfer. When the TS7001

is operated in Mode 1(its default power management mode), the CS pin also acts as the

shutdown pin in that the TS7001 is powered-down when the CS pin is logic high.

2

VDD

the VDD pin also serves as the TS7001’s voltage reference source during conversions. For

optimal

performance,

the

VDD

pin

should

be

bypassed

to

GND

with

a

10-µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor.

3

GND

Analog Ground Pin: The GND pin is the ground reference point for all TS7001 internal

circuitry. In systems with separate AGND and DGND planes, the TS7001’s GND pin

should be connected to the AGND plane.

4

AIN1/VREF

Analog Input Channel 1/External VREF Input: In single-channel mode, the AIN1/VREF pin

is configured as VREFIN/OUT. In this mode, the TS7001’s internal 2.5V reference can be

accessed or an external reference can be applied to this pin thereby overriding the internal

reference. The reference voltage range for an externally-applied reference is 1.2V to VDD.

In two-channel mode, the AIN1/VREF pin operates as a second analog input channel,

AIN1. The input voltage range on AIN1 is 0 to VDD.

5

AIN0

Analog Input Channel 0: In single-channel operation, AIN0 is the TS7001’s analog input

with an input voltage range of 0V to VREF. In two-channel operation, the AIN0 pin exhibits

an analog input range of 0V to VDD.

6

DIN

Serial Data Input: Serial data to be loaded into the TS7001’s control register is applied at

the DIN pin. Serial data is loaded into the ADC from the host processor on low-to-high

SCLK transitions (see the Control Register section for additional information). Configuring

the TS7001 as a single-channel, read-only ADC can be achieved by hard-wiring the DIN

pin to GND or by applying a logic LOW at all times at the DIN pin.

7

DOUT

Serial Data Output: The TS7001’s conversion result is available on this pin. Serial data is

transferred out of the TS7887 on high-to low transitions of SCLK. The 12-bit conversion

result is comprised of four leading zeros followed by the 12 bits of conversion data

formatted MSB first. Thus, a total of 16 SCLK high-to-low transitions transfers the

conversion result to the host processor as shown in the corresponding timing diagram of

Figure 14.

8

SCLK

Serial-Clock Input: SCLK is used for (3) purposes: a) to load serial data from the host

processor into the TS7001’s control register on low-to-high SCLK transitions; b) to transfer

the 12-bit conversion result to the host processor on high-to-low SCLK transitions; and c)

to control the TS7001’s conversion process.