ADS5474IPFPR datasheet(21/41 Pages) TI1

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ADS5474

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SLAS525C – JULY 2007 – REVISED JANUARY 2016

Feature Description (continued)

a measured 10-pF parasitic board capacitance to ground on each LVDS line (or 5-pF differential parasitic

capacitance). When setting the time relationship between DRY and DATA at the receiving device, it is generally

recommended that setup time be maximized, but this partially depends on the setup and hold times of the device

receiving the digital data (like an FPGA or Field Programmable Field Array). Since DRY and DATA are

coincident, it will likely be necessary to delay either DRY or DATA such that setup time is maximized.

Referencing Figure 1, the polarity of DRY with respect to the sample N data output transition is undetermined

because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a

frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N and

the polarity of DRY could invert when power is cycled off/on or when the power-down pin is cycled. Data capture

from the transition and not the polarity of DRY is recommended, but not required. If the synchronization of

multiple ADS5474 devices is required, it might be necessary to use a form of the CLKIN signal rather than DRY

to capture the data.

The DRY frequency is identical on the ADS5474 and ADS5463 devices (where DRY equals ½ the CLK

frequency), but different on the pin-similar ADS5444 and ADS5440 devices (where DRY equals the CLK

frequency). The LVDS outputs all require an external 100-

Ω load between each output pair in order to meet the

expected LVDS voltage levels. For long trace lengths, it may be necessary to place a 100-

Ω load on each digital

output as close to the ADS5474 device as possible and another 100-

Ω differential load at the end of the LVDS

transmission line to provide matched impedance and avoid signal reflections. The effective load in this case

reduces the LVDS voltage levels by half.

The OVR output equals a logic high when the 14-bit output word attempts to exceed either all 0s or all 1s. This

flag is provided as an indicator that the analog input signal exceeded the full-scale input limit of approximately

2.2 VPP (± gain error). The OVR indicator is provided for systems that use gain control to keep the analog input

signal within acceptable limits.

7.4 Device Functional Modes

7.4.1 External Voltage Reference

For systems that require the analog signal gain to be adjusted or calibrated, this can be performed by using an

external reference. The dependency on the signal amplitude to the value of the external reference voltage is

characterized typically by Figure 38 (VREF = 2.4 V is normalized to 0 dB as this is the internal reference

voltage). As can be seen in the linear fit, this equates to approximately –0.3 dB of signal adjustment per 100 mV

of reference adjustment. The range of allowable variation depends on the analog input amplitude that is applied

to the inputs and the desired spectral performance, as can be seen in the performance versus external reference

graphs in Figure 39 and Figure 40. As the applied analog signal amplitude is reduced, more variation in the

reference voltage is allowed in the positive direction (which equates to a reduction in signal amplitude), whereas

an adjustment in reference voltage below the nominal 2.4 V (which equates to an increase in signal amplitude) is

not recommended below approximately 2.35 V. The power consumption versus reference voltage and operating

temperature should also be considered, especially at high ambient temperatures, because the lifetime of the

device is affected by internal junction temperature (see Figure 48).

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