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LAN8820 Scheda tecnica(PDF) 74 Page - Microchip Technology |
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LAN8820 Scheda tecnica(HTML) 74 Page - Microchip Technology |
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74 / 83 page ![]() LAN8820/LAN8820I DS00001871B-page 74 2009-2015 Microchip Technology Inc. 5.5.7 JTAG TIMING This section specifies the JTAG timing of the device. Please refer to Section 3.9.7, "IEEE 1149.1 (JTAG) Boundary Scan," on page 30 for additional details. FIGURE 5-10: JTAG TIMING TABLE 5-19: JTAG TIMING VALUES Symbol Description Min Max Units Notes ttckp TCK clock period 66.67 ns ttckhl TCK clock high/low time ttckp*0.4 ttckp*0.6 ns tsu TDI, TMS setup to TCK rising edge 10 ns th TDI, TMS hold from TCK rising edge 10 ns tdov TDO output valid from TCK falling edge 16 ns tdohinvld TDO output invalid from TCK falling edge 0 ns TCK (Input) TDI, TMS (Inputs) ttckhl ttckp ttckhl tsu th tdov TDO (Output) tdohinvld |
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