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SIO1007 Scheda tecnica(PDF) 14 Page - Microchip Technology

Il numero della parte SIO1007
Spiegazioni elettronici  LPC Super I/O LPC IrDA Hot Docking Chip with UART
PDF  108 Pages
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Produttore elettronici  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

SIO1007 Scheda tecnica(HTML) 14 Page - Microchip Technology

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SIO1007
DS00002020A-page 14
 2005 - 2015 Microchip Technology Inc.
6.0
SUPER I/O REGISTERS
The address map, shown below in Table 6-1, shows the addresses of the different blocks of the Super I/O immediately
after power up. The base addresses of the following blocks can be moved via the configuration registers: Serial Port
Com 1, Serial Port Com 2, Synchronous Communications Engine (SCE), CIRCC2, Runtime Registers, Configuration,
LPC Docking. Some addresses are used to access more than one register.
6.1
Host Processor Interface (LPC)
The host processor communicates with the SIO1007 through a series of read/write registers via the LPC interface. The
port addresses for these registers are shown in Table 6-1. Register access is accomplished through I/O cycles or DMA
transfers. All registers are 8 bits wide. Section 18.5, "Logical Device Base I/O Address and Range," on page 85 for base
address, activation and power control for each logical device.
Note 1: Refer to the configuration register descriptions for setting the base address.
2: Serial Port COM 2 block provides IR Support (FIR and CIR) but does not have standard 8 pin UART inter-
face.
3: The Runtime Register Block includes all PME, SMI, and GP data registers.
TABLE 6-1:
SUPER I/O BLOCK ADDRESSES
Address
Block Name
Notes
Base+(0-7)
Serial Port Com 1
ACE:Base1+(0-7)
SCE:Base2+(0-7)
Serial Port Com 2
SCE
IR Support
FIR and CIR
Base+(0-7)
CIRCC2
Consumer IR Support NEC PPM and
RC5
Base + (0-F)
Runtime Registers
Base + (0-1)
Configuration
Base + 0
LPC Docking



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