C161S datasheet(21/75 Pages) INFINEON

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C161S

Functional Description

Data Sheet

V1.0, 2003-11

The C161S also provides an excellent mechanism to identify and to process exceptions

or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware

traps cause immediate non-maskable system reaction which is similar to a standard

interrupt service (branching to a dedicated vector table location). The occurrence of a

hardware trap is additionally signified by an individual bit in the trap flag register (TFR).

Except when another higher prioritized trap service is in progress, a hardware trap will

interrupt any actual program execution. In turn, hardware trap services can normally not

be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4

Hardware Trap Summary

Exception Condition

Trap

Flag

Trap

Vector

Location

Trap

Number

Trap

Priority

Reset Functions:

•

Hardware Reset

•

Software Reset

•

W-dog Timer Overflow

–

RESET

00’0000

III

Class A Hardware Traps:

•

Non-Maskable

Interrupt

•

Stack Overflow

•

Stack Underflow

NMI

STKOF

STKUF

NMITRAP

STOTRAP

STUTRAP

00’0008

00’0010

00’0018

Class B Hardware Traps:

•

Undefined Opcode

•

Protected Instruction

Fault

•

Illegal Word Operand

Access

•

Illegal Instruction

Access

•

Illegal External Bus

Access

UNDOPC

PRTFLT

ILLOPA

ILLINA

ILLBUS

BTRAP

00’0028

Reserved

–

[2C

H –

[0B

H –

–

Software Traps

•

TRAP Instruction

––

Any

[00’0000

H –

00’01FC

in steps of

Any

[00

H –

Current

CPU

Priority

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