DocID026560 Rev 2

7/16

MP34DT02

Application recommendations

16

Power supply decoupling capacitors (100 nF ceramic, 10 µF ceramic) should be placed as

near as possible to pin 1 of the device (common design practice).

The L/R pin must be connected to Vdd or GND (refer to Table 5).

3.1

Timing characteristics

Figure 5. Timing waveforms

Table 5. Timing characteristics

Parameter

Description

Min

Max

Unit

Clock frequency for normal mode

1

3.25

MHz

Clock frequency for power-down mode

0.23

MHz

Clock period for normal mode

308

1000

ns

Data enabled on DATA line, L/R pin = 1

1.

From design simulations

ns

Data disabled on DATA line, L/R pin = 1

16(1)

ns

Data enabled on DATA line, L/R pin = 0

18(1)

ns

Data disabled on DATA line, L/R pin = 0

16(1)

ns

High Z

High Z

High Z

High Z

T

L,EN

R,DIS

R,EN

T

L,DIS

T

T

T

CLK

AM045165v1

CLK

PDM R

PDM L