74F169SC datasheet(2/8 Pages) NSC

2 / 8 page

Connection Diagrams

Pin Assignment for

DIP SOIC and Flatpak

TLF9488 – 1

Pin Assignment

for LCC

TLF9488 – 2

Unit LoadingFan Out

54F74F

Pin Names

Description

Input IIH IIL

HIGHLOW

Output IOH IOL

CEP

Count Enable Parallel Input (Active LOW)

1010

20 mA b06 mA

CET

Count Enable Trickle Input (Active LOW)

1020

20 mA b12 mA

Clock Pulse Input (Active Rising Edge)

1010

20 mA b06 mA

P0–P3

Parallel Data Inputs

1010

20 mA b06 mA

Parallel Enable Input (Active LOW)

1010

20 mA b06 mA

Up-Down Count Control Input

1010

20 mA b06 mA

Q0–Q3

Flip-Flop Outputs

50333

1 mA20 mA

Terminal Count Output (Active LOW)

50333

1 mA20 mA

Functional Description

The ’F169 uses edge-triggered J-K type flip-flops and has

no constraints on changing the control or data input signals

in either state of the clock The only requirement is that the

various inputs attain the desired state at least a setup time

before the rising edge of the clock and remain valid for the

recommended hold time thereafter The parallel load opera-

tion takes precedence over other operations as indicated in

the Mode Select Table When PE is LOW the data on the

P0–P3 inputs enters the flip-flops on the next rising edge of

the clock In order for counting to occur both CEP and CET

must be LOW and PE must be HIGH the UD input then

determines the direction of counting The Terminal Count

(TC) output is normally HIGH and goes LOW provided that

CET is LOW when a counter reaches zero in the Count

Down mode or reaches 15 for the ’F169 in the Count Up

mode The TC output state is not a function of the Count

Enable Parallel (CEP) input level Since the TC signal is de-

rived by decoding the flip-flop states there exists the possi-

bility of decoding spikes on TC For this reason the use of

TC as a clock signal is not recommended (see logic equa-

tions below)

1) Count Enable e CEP

CET PE

2) Up (’F169) TC e Q0 Q1 Q2 Q3 (Up) CET

3) Down TC e Q0 Q1 Q2 Q3 (Down) CET

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