VS6663CC datasheet(14/63 Pages) STMICROELECTRONICS

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Functional description

VS6663CC

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Doc ID028526 Rev 1

3.2.1

Power-up procedure

The digital and analog supply voltages can be powered up in any order, for example, VDIG

then VANA or VANA then VDIG.

On power-up the on-chip power-on reset cell ensures that the CCI register values are

initialized correctly to their default values.

The EXTCLK clock can either be initially low and then enabled during software standby

mode or EXTCLK can be a free running clock.

The power-up sequence timing constraints are shown in Table 6.

Table 6. Power-up sequence timing constraints

Symbol

Parameter

Min.

Max.

Units

VANA rising – VDIG rising

VANA and VDIG may rise in any

order. The rising separation can

vary from 0 ns to indefinite.

VDIG rising – VANA rising

VDIG / VANA rising –

XSHUTDOWN rising

XSHUTDOWN must rise later

than or coincident with the later

rising supply (VDIG or VANA)

µs

XSHUTDOWN – First I2C

transaction

2400

EXTCLK cycles

Minimum number of EXTCLK cycles

prior to the first I2C transaction

2400

EXTCLK cycles

PLL start up/lock time

Entering streaming mode – First

frame start sequence (fixed part)

-ms

Entering streaming mode – First

frame start sequence (variable part)

= Integration time

The delay is the coarse

integration time value.

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