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S3P72P9 Scheda tecnica(PDF) 70 Page - Samsung semiconductor |
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S3P72P9 Scheda tecnica(HTML) 70 Page - Samsung semiconductor |
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70 / 225 page ![]() MEMORY MAP S3C72P9/P72P9 (Preliminary Spec) 4-20 IMODK — External Key Interrupt Mode Register CPU FB6H Bit 3 2 1 0 Identifier "0" IMODK.2 IMODK.1 IMODK.0 RESET RESET Value 0 0 0 0 Read/Write W W W W Bit Addressing 4 4 4 4 IMODK.3 Bit 3 0 Always logic zero IMODK.2 External Key Interrupt Edge Detection Selection Bit 0 Falling edge detection 1 Rising edge detection IMODK.1 – .0 External Key Interrupt Mode Control Bits 0 0 Disable key interrupt 0 1 Enable edge detection at K0–K3 pins 1 0 Enable edge detection at K4-K7 pins 1 1 Enable edge detection at K0–K7 pins NOTES: 1. To generate a key interrupt, all of the selected pins must be configured to input mode. If any one of the selected pins is configured to output mode, only falling edge can be detected. 2. To generate a key interrupt, all of the selected pins must be at input high state for falling edge detection, or all of the selected pins must be at input low state for rising edge detection. If any one of them or more is at input low state or input high state, the interrupt may be not occurred at falling edge or rising edge. 3. To generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. And then, select edge detection and pins by setting IMODK register. |
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