SWCS049 datasheet(45/119 Pages) TI1

45 / 119 page

TPS659110, TPS659112, TPS659113

TPS659114, TPS659118, TPS6591133

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SWCS049Q – JUNE 2010 – REVISED MARCH 2016

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Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133

Detailed Description

6.3.1.1

Device POWER ON Enable Conditions

The device POWER ON enable conditions are as follows:

•

None of the device POWER ON disable conditions are met.

•

PWRON signal low level

•

Or PWRHOLD signal high level

•

Or DEV_ON control bit set to 1 (default inactive)

•

Or interrupt flag active (default INT1 low) generates a POWER ON enable condition during a fixed

delay (tDOINT1 pulse duration defined in Section 5.23.2, Power Control Timing). Interrupt sources

expected (if enabled), when the device is off:

–

RTC alarm interrupt

–

First-time input voltage rising above the VMBHI threshold (depending on the boot mode used) and

input voltage > VMBCH threshold. The interrupt corresponding to this last condition is VMBCH_IT

in the INT_STS_REG register.

–

Or HDRST reset release generates a POWER ON enable condition during a fixed delay tDOINT1

Interrupt flag active generates a POWER ON enable condition pulse of length tDOINT1 only when the device

is in the OFF state (when the NRESPWRON signal is low). The POWER ON enable condition pulse

occurs only if the interrupt status bit is initially low (no previous interrupt pending in the status register).

The interrupt status register must first be cleared to allow device power off during the tDOINT1 pulse

duration.

GPIO2 cannot be used to turn on the device, even if its associated interrupt is not masked. The GPIO0,

GPIO1, GPIO3, GPIO4, or GPIO5 signals can be used to turn on the device, if its associated interrupt is

not masked.

NOTE

The watchdog interrupt is not a power-on event, but can wake up the device from sleep

mode.

6.3.1.2

Device POWER ON Disable Conditions

Device POWER ON disable conditions are as follows:

•

PWRON signal low level during more than the long-press delay: PWON_LP_DELAY (can be disabled

though register programming). The interrupt corresponding to this condition is PWRON_LP_IT in the

INT_STS_REG register.

•

Or die temperature has reached the thermal shutdown threshold (THERM_TS = 1).

•

Or DEV_OFF or DEV_OFF_RST control bit is set to 1 (DEV_OFF value is cleared when the device is

in OFF state).

NOTE

If the DEV_ON bit is set to 1, after switch-off, the device switches back on. To keep the

device off, DEV_ON must be cleared first.

6.3.1.3

Device SLEEP Enable Conditions

Device SLEEP enable conditions are as follows:

•

SLEEP signal low level (default, or high level depending on the programmed polarity)

•

And DEV_SLP control bit is set to 1.

•

And interrupt flag inactive (default INT1 high): no nonmasked interrupt is pending.

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