ADC08060 datasheet(13/19 Pages) NSC

13 / 19 page

Timing Diagram

Functional Description

The ADC08060 uses a new, unique architecture that

achieves over 7.4 effective bits at input frequencies up to

30 MHz.

The analog input signal that is within the voltage range set by

RT and VRB is digitized to eight bits. Output format is

straight binary. Input voltages below V

RB will cause the

output word to consist of all zeroes. Input voltages above

RB will cause the output word to consist of all ones.

Incorporating a switched capacitor bandgap, the ADC08060

exhibits a power consumption that is proportional to fre-

quency, limiting power consumption to what is needed at the

clock rate that is used. This and its excellent performance

over a wide range of clock frequencies makes it an ideal

choice as a single ADC for many 8-bit needs.

Data is acquired at the falling edge of the clock and the

digital equivalent of that data is available at the digital out-

puts 2.5 clock cycles plus t

OD later. The ADC08060 will

convert as long as the clock signal is present. The device is

in the active state when the Power Down pin (PD) is low.

When the PD pin is high, the device is in the power down

mode, where the output pins hold the last conversion before

the PD pin went high and the device consumes just 1 mW.

Applications Information

1.0 REFERENCE INPUTS

The reference inputs V

RT and VRB are the top and bottom of

the reference ladder, respectively. Input signals between

these two voltages will be digitized to 8 bits. External volt-

ages applied to the reference input pins should be within the

range specified in the Operating Ratings table (1.0V to (V

A +

0.1V) for V

RT and 0V to (VRT − 1.0V) for VRB). Any device

used to drive the reference pins should be able to source

sufficient current into the V

RT pin and sink sufficient current

from the V

RB pin.

20006231

FIGURE 1. ADC08060 Timing Diagram

ADC08060 Scheda tecnica(PDF) 13 Page - National Semiconductor (TI)

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