PI6C485352

2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer

6

PI6C485352 Rev. A

01/24/13

V

1KΩ

C1

Single Ended

Clock Input

CC

CLK1

R2

R1

1KΩ

nCLK1

V_REF

0.1μF

Applications Information

Wiring the differential input to accept single ended levels

Figure 1 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VCC/2 is gener-

ated by the bias resistors R1, R2 and C1. This bias circuit should be placed as close as possible to the input pin. The ratio of R1 and

R2 should be adjusted to postion the V_REF at the center of the input voltage swing. For example, if the input clock swing is 2.5V

and VCC = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.

Figure 1: Single-ended Signal Driving Differential Input

13-0003