ADC12138CIWM datasheet(9/41 Pages) NSC

9 / 41 page

AC Electrical Characteristics (Continued)

The following specifications apply for (V

+ =V

A+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V

common-mode voltage) or (V

+ =V

A+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V

common-mode voltage), V

REF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+

≤ 25Ω,f

CK =fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA =TJ =

MIN to TMAX; all other limits TA =TJ = 25˚C. (Note 17)

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note

10)

(Note

11)

(Limits)

Acquisition Time

6 Cycles Programmed

6(t

CK)

6(t

CK)

(min)

(Note 19)

7(t

CK)

(max)

1.2

µs (min)

1.4

µs (max)

10 Cycles Programmed

10(t

CK)

10(t

CK)

(min)

11(t

CK)

(max)

2.0

µs (min)

2.2

µs (max)

18 Cycles Programmed

18(t

CK)

18(t

CK)

(min)

19(t

CK)

(max)

3.6

µs (min)

3.8

µs (max)

34 Cycles Programmed

34(t

CK)

34(t

CK)

(min)

35(t

CK)

(max)

6.8

µs (min)

7.0

µs (max)

CAL

Self-Calibration Time

4944(t

CK)

4944(t

CK)

(max)

988.8

µs (max)

Auto-Zero Time

76(t

CK)

76(t

CK)

(max)

15.2

µs (max)

SYNC

Self-Calibration or

2(t

CK)

2(t

CK)

(min)

Auto-Zero Synchronization

3(t

CK)

(max)

Time from DOR

0.40

µs (min)

0.60

µs (max)

DOR

DOR High Time when CS is Low

9(t

SK)

9(t

SK)

(max)

Continuously for Read Data and Software

Power Up/Down

1.8

µs (max)

CONV

CONV Valid Data Time

8(t

SK)

8(t

SK)

(max)

1.6

µs (max)

AC Electrical Characteristics

The following specifications apply for (V

+ =V

A+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V

common-mode voltage) or (V

+ =V

A+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V

common-mode voltage), V

REF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+

≤ 25Ω,f

CK =fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA =TJ =

MIN to TMAX; all other limits TA =TJ = 25˚C. (Note 17) (Continued)

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 10)

(Note 11)

(Limits)

HPU

Hardware Power-Up Time, Time from

500

700

µs (max)

PD Falling Edge to EOC Rising Edge

SPU

Software Power-Up Time, Time from

Serial Data Clock Falling Edge to

500

700

µs (max)

EOC Rising Edge

ACC

Access Time Delay from

ns (max)

CS Falling Edge to DO Data Valid

ADC12138CIWM Scheda tecnica(PDF) 9 Page - National Semiconductor (TI)

ADC12138CIWM Scheda tecnica(HTML) 9 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Scheda tecnica Scarica

Link URL