MB9DF564LLE datasheet(6/109 Pages) SPANSION

6 / 109 page

D at aS he e t

May 15, 2015, MB9D560_DS708-00001-3v0-E

CONFIDENTIAL

2. Features

Function

Description

Technology

−

CMOS 90nm technology

CPU

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ARM Cortex®-R5F

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32-bit ARM architecture

−

2-instruction issuance super scalar

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8-stage pipeline

−

ARMv7 / Thumb®-2 instruction set

−

Floating-Point Unit (FPU)

Double precision

−

Memory protection Unit (MPU)

16 area

−

ECC support for the TCM port

1-bit error correction, 2-bit error detection ECC (SEC-DED)

−

TCM port

2 TCM ports

−

ATCM port

−

BTCM 2 ports (B0TCM, B1TCM)

−

VIC port

Low latency interrupt

−

AXI master interface

64-bit AXI interface (instruction / data access)

32-bit AXI interface (I/O access)

−

AXI slave interface

64-bit AXI interface (accessible to TCM port)

−

CPU configuration

2 CPUs (AMP operation)

−

Operating frequency

Maximum 200 MHz

−

Trace with ETM-R5

Debugging

−

ARM CoreSightTM Technology

Each CPU embedded Embedded Trace Macro (ETM), trace support of CPU operation

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Debugging interface

JTAG (5 pin )

Support clock : maximum 20 MHz

−

Debugging security support

128-bit security key (Device security key)

−

Wakeup function on JTAG

Operation mode

−

User mode

Normal mode (internal memory activation)

−

Serial writer mode

Clock control

−

Internal clock source

Fast-CR oscillation (8 MHz)

Slow-CR oscillation (100 kHz)

−

External oscillation input

Main clock input

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Embedded PLL

Main PLL (Multiplying clock of main oscillation )

−

Oscillator stabilized timer

Support oscillator stabilized timer for all clock source independently

After a lapse of oscillator stabilized time, it is able to use source clock timer (Except PLL for FlexRay/RDC)

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