MB9DF565LLE datasheet(72/109 Pages) SPANSION

Il numero della parte	MB9DF565LLE

Spiegazioni elettronici	This document states the current technical specifications regarding

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D at aS he e t

May 15, 2015, MB9D560_DS708-00001-3v0-E

CONFIDENTIAL

− Guaranteed operation range Internal operation clock frequency vs. Power supply voltage

Internal operation clock frequency FCD0_CLK(MHz)

200

3.7

5.5

4.5

1.3

1.1

Recommended guaranteed operation range:

Guaranteed operation range:

PLL guaranteed operation range:

1.09

Note: The CPU will be reset at the power supply voltage of the low-voltage detection setting voltage or less.

− Oscillation clock frequency vs. Internal operation clock frequency

Oscillation Clock

Frequency

Main Clock

PLL Multiplying

Setting

PLL Output Divider

Setting

PLL Clock

4 MHz

100

200 MHz

8 MHz

200 MHz

8 MHz

4 MHz

100

200 MHz

16 MHz

200 MHz

16 MHz

8 MHz

200 MHz

− Example of oscillation circuit

Note: when configuring the oscillator circuit, it is recommended to ask matching evaluation of the circuit to oscillator

manufacturers for the design.

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