Integrated

Circuit

Systems, Inc.

8305AG

www.icst.com/products/hiperclocks.html

REV. B FEBRUARY 26, 2004

1

ICS8305

The ICS8305 is a low skew, 1-to-4, Differential/

LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a

member of the HiPerClockS ™ family of High

Performance Clock Solutions from ICS. The

ICS8305 has selectable clock inputs that accept

either differential or single ended input levels.The clock enable is

internally synchronized to eliminate runt pulses on the outputs

during asynchronous assertion/deassertion of the clock enable

pin. Outputs are forced LOW when the clock is disabled. A sepa-

rate output enable pin controls whether the outputs are in the

active or high impedance state.

Guaranteed output and part-to-part skew characteristics make

the ICS8305 ideal for those applications demanding well de-

fined performance and repeatability.

HiPerClockS™

ICS

GND

OE

CLK_EN

CLK

nCLK

CLK_SEL

LVCMOS_CLK

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Q0

Q1

GND

Q2

Q3

GND

ICS8305

16-Lead TSSOP

4.4mm x 3.0mm x 0.92mm package body

G Package

Top View

• 4 LVCMOS/LVTTL outputs

• Selectable differential or LVCMOS/LVTTL clock inputs

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• LVCMOS_CLK supports the following input types:

LVCMOS, LVTTL

• Maximum output frequency: 350MHz

• Output skew: 35ps (maximum)

• Part-to-part skew: 700ps (maximum)

• Additive phase jitter, RMS: 0.04ps (typical)

• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

LVCMOS_CLK

CLK

nCLK

CLK_SEL

Q0

Q1

Q2

Q3

0

1

CLK_EN

OE

D

Q

LE

0

1