CLC451 datasheet(9/12 Pages) NSC

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Figure 8: Dual Supply, Av = +1V/V Configuration

Figure 9: Dual Supply, Av = +2V/V Configuration

Bandwidth vs. Output Amplitude

The bandwidth of the CLC451 is at a maximum for

output voltages near 1Vpp. The bandwidth decreases

for smaller and larger output amplitudes. Refer to the

Frequency Response vs. Vo plots.

Load Termination

The CLC451 can source and sink near equal amounts of

current. For optimum performance, the load should be

tied to Vcm.

Driving Cables and Capacitive Loads

When driving cables, double termination is used to

prevent reflections. For capacitive load applications, a

small series resistor at the output of the CLC451 will

improve

stability

and

settling

performance. The

Frequency Response vs. CL and Recommended Rs

vs. CL plots, in the typical performance section, give the

recommended series resistance value for optimum

flatness at various capacitive loads.

Transmission Line Matching

One method for matching the characteristic impedance

(Zo) of a transmission line or cable is to place the

appropriate resistor at the input or output of the amplifier.

Figure 10 shows typical inverting and non-inverting

circuit configurations for matching transmission lines.

Non-inverting gain applications:

Connect pin 2 as indicated in the table in the

Closed Loop Gain Selection section.

Make R1, R2, R6, and R7 equal to Zo.

Use R3 to isolate the amplifier from reactive

loading caused by the transmission line,

or by parasitics.

Inverting gain applications:

Connect R3 directly to ground.

Make the resistors R4, R6, and R7 equal to Zo.

Make R5 II Rg = Zo.

The input and output matching resistors attenuate the

signal by a factor of 2, therefore additional gain is needed.

Use C6 to match the output transmission line over a

greater frequency range. C6 compensates for the increase

of the amplifier’s output impedance with frequency.

Figure 10: Transmission Line Matching

Power Dissipation

Follow these steps to determine the power consumption

of the CLC451:

1. Calculate the quiescent (no-load) power:

Pamp = ICC (VCC - VEE)

2. Calculate the RMS power at the output stage:

Po = (VCC - Vload) (Iload), where Vload and Iload

are the RMS voltage and current across the

external load.

3. Calculate the total RMS power:

Pt = Pamp + Po

The maximum power that the DIP, SOIC, and SOT

packages can dissipate at a given temperature is

illustrated in Figure 11. The power derating curve for

any CLC451 package can be derived by utilizing the

following equation:

where

Tamb = Ambient temperature (°C)

JA = Thermal resistance, from junction to ambient,

for a given package (°C/W)

(175

Tamb

°−

)

0.1

µF

6.8

µF

Vin

VCC

CLC451

Ω

0.1

µF

6.8

µF

VEE

0.1

µF

6.8

µF

Vin

VCC

CLC451

Ω

0.1

µF

6.8

µF

VEE

V2 +-

CLC451

Ω

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