CLC533AMC datasheet(6/9 Pages) NSC

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above 1/2 the sampling frequency will be aliased into

the baseband and will corrupt the signal of interest.

When the CLC533 is switched from one channel to

another, the output slews rapidly until it arrives at

the new signal. This high slew rate signal can capac-

itively couple into other nodes in the circuit and can

have a detrimental effect on overall performance.

Since

coupling

through

stray

capacitance

and

inductances decreases with decreasing dV/dt, the

slew rate should be minimized consistent with system

throughput requirements.

Figure 1: ECL Level Channel SELECT Configuration

Figure 2: TTL/CMOS Level Channel

SELECT Configuration

Output Load

The final frequency response that is realized is a result of

both the compensation capacitor and the load that the

CLC533 is driving. Figure 3 below shows the effect that

CCOMP has on bandwidth for a fixed load. Graphs on the

preceding pages demonstrate the effect of CCOMP on

pulse response and settling time, and the optimum value

of CCOMP to maximize bandwidth for various amounts of

resistive loading. Because there are so many factors that

go into determining the optimum value of CCOMP it is

recommended that once a value is selected, the

application circuit be built up and larger and smaller

compensation capacitors be tried to determine the best

value for that particular circuit.

The output load that the CLC533 is driving has an effect

on the harmonic distortion of the device as well as

frequency response. Distortion is minimized with a 500

Ω

load. When driving components with a high input

impedance, addition of a load resistor can improve the

performance. If the load is capacitive in nature, it should

be isolated from the CLC533 output via a series resistor.

The recommended series resistor Rs, for various

capacitive loads CL, can be found by referring to the

“Recommended Compensation Cap vs. Load” plot in the

“Typical Performance” section.

Figure 3

Power Supplies and Grounding

any

circuit

there

are

connections

between

components that are not desired. Some of the most com-

mon of these are the connections made through the

power supply and grounding network. The goal in laying

out the power and ground network for a mixed mode

circuit is to minimize the impedance from the power pins

to the supply, and minimize the impedance of the ground

network.

To minimize impedance of the ground and power nets,

use the heaviest possible traces and ground planes for

minimizing the DC impedance. To further reduce the

supply impedance at higher frequencies, a 6 to 10

µF

capacitor should be placed between supply lines and

ground. At very high frequencies, the inductance in the

traces becomes significant and 0.01 to 0.1

µF bypass

capacitors need to be placed as close to each power pin

as is practical. To reduce the negative effects of ground

impedances that will exist, consider the paths that ground

currents must take to get from the various devices on the

circuit card to the power supply. To achieve good system

performance, it is vital that large currents and high-speed

time varying currents like CMOS signals, be kept away

from precision analog components. This can be achieved

through layout of the power and ground nets. Using a

ground plane split between analog and digital sections of

the circuit forces all of the ground current from the digital

circuits to go directly to the power connector without

straying to the analog side of the card.

Optimizing for Channel-to-Channel Isolation

Although

the

CLC533

has

excellent

channel-to-

channel isolation, if there is cross talk between the input

signals

before

they

reach

the

CLC533,

the

multiplexer will faithfully pass these corrupted signals

through to its output and dutifully take the blame for poor

Small Signal Bandwidth (30MHz/div)

Ω

130

Ω

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