AS7C256

AS7C256L

6

2. This parameter is sampled and not 100% tested.

3. For test conditions, see AC Test Conditions, Figures A, B, C.

5. This parameter is guaranteed but not tested.

6. WE is HIGH for read cycle.

7. CE and OE are LOW for read cycle.

8. Address valid prior to or coincident with CE transition LOW.

9. All read cycle timings are referenced from the last valid address to the first transitioning address.

10. CE or WE must be HIGH during address transitions.

11. All write cycle timings are referenced from the last valid address to the first transitioning address.

Parameter

Symbol

Test Conditions

Min

Max

Unit

CE

2.0

–

V

Data Retention Current

–

150

Chip Enable to Data Retention Time

0–

ns

Operation Recovery Time

–ns

Input Leakage Current

–1

DATA RETENTION CHARACTERISTICS

(L Version Only)

DATA RETENTION WAVEFORM

(L Version Only)

CE

Data retention mode

4.5V

4.5V

AS7C256-07

AC TEST CONDITIONS

255

Ω

– Output load: see Figure B,

– Input pulse level: GND to 3.0V. See Figure A.

– Input rise and fall times: 5 ns. See Figure A.

– Input and output timing reference levels: 1.5V.

5 pF*

480

Ω

GND

+5V

168

Ω

Thevenin Equivalent:

+1.728V

255

Ω

30 pF*

480

Ω

GND

+5V

Figure B: Output Load

*including scope

10%

90%

10%

90%

GND

+3.0V

Figure A: Input Waveform

and jig capacitance

AS7C256-08

AS7C256-09

AS7C256-10

NOTES