Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
16
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
Table 4:
Pin-out 28 Pin
Name
I/O
Pin
Description
P0[7]
I/O
1 Port 0[7] (Analog Input)
P0[5]
I/O
2
Port 0[5] (Analog Input/ Out-
put)
P0[3]
I/O
3
Port 0[3] (Analog Input/ Out-
put)
P0[1]
I/O
4 Port 0[1] (Analog Input)
P2[7]
I/O
5 Port 2[7]
P2[5]
I/O
6 Port 2[5]
P2[3]
I/O
7
Port 2[3] (Non-Multiplexed
Analog Input)
P2[1]
I/O
8
Port 2[1] (Non-Multiplexed
Analog Input)
SMP
O
9 Switch Mode Pump
P1[7]
I/O
10 Port 1[7]
P1[5]
I/O
11 Port 1[5]
P1[3]
I/O
12 Port 1[3]
P1[1]
I/O
13 Port 1[1] / XtalIn / SCLK
Vss
Power
14 Ground
P1[0]
I/O
15 Port 1[0] / XtalOut / SDATA
P1[2]
I/O
16 Port 1[2]
P1[4]
I/O
17 Port 1[4]
P1[6]
I/O
18 Port 1[6]
XRES
I
19 External Reset
P2[0]
I/O
20
Port 2[0] (Non-Multiplexed
Analog Input)
P2[2]
I/O
21
Port 2[2] (Non-Multiplexed
Analog Input)
P2[4]
I/O
22 Port 2[4] / External AGNDIn
P2[6]
I/O
23 Port 2[6] / External VREFIn
P0[0]
I/O
24 Port 0[0] (Analog Input)
P0[2]
I/O
25
Port 0[2] (Analog Input/Out-
put)
P0[4]
I/O
26
Port 0[4] (Analog Input/Out-
put)
P0[6]
I/O
27 Port 0[6] (Analog Input)
Vcc
Power
28 Supply Voltage
Figure 4: 26443 PDIP/SOIC/SSOP
Table 5:
Pin-out 44 Pin
Name
I/O
Pin
Description
P2[5]
I/O
1 Port 2[5]
P2[3]
I/O
2
Port 2[3] (Non-Multiplexed
Analog Input)
P2[1]
I/O
3
Port 2[1] (Non-Multiplexed
Analog Input)
P3[7]
I/O
4 Port 3[7]
P3[5]
I/O
5 Port 3[5]
P3[3]
I/O
6 Port 3[3]
P3[1]
I/O
7 Port 3[1]
SMP
O
8 Switch Mode Pump
P4[7]
I/O
9 Port 4[7]
P4[5]
I/O
10 Port 4[5]
P4[3]
I/O
11 Port 4[3]
P4[1]
I/O
12 Port 4[1]
P1[7]
I/O
13 Port 1[7]
P1[5]
I/O
14 Port 1[5]
P1[3]
I/O
15 Port 1[3]
P1[1]
I/O
16 Port 1[1] / XtalIn / SCLK
Vss
Power
17 Ground
P1[0]
I/O
18 Port 1[0] / XtalOut / SDATA
P1[2]
I/O
19 Port 1[2]
P1[4]
I/O
20 Port 1[4]
P1[6]
I/O
21 Port 1[6]
P4[0]
I/O
22 Port 4[0]
P4[2]
I/O
23 Port 4[2]
P4[4]
I/O
24 Port 4[4]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
P1[7]
P1[5]
P1[3]
XtalIn/SCLK/P1[1]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P1[6]
P1[4]
P1[2]
P1[0]/XtalOut/SDATA
Xres
P2[6]/External V
ref
Vcc
P2[4]/External AGND
Vss
Italian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
