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COP884CS Scheda tecnica(PDF) 46 Page - National Semiconductor (TI) |
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COP884CS Scheda tecnica(HTML) 46 Page - National Semiconductor (TI) |
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46 / 53 page ![]() Instruction Execution Time Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. Bytes and Cycles per Instruction The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle. Arithmetic and Logic Instructions [B] Direct Immed. ADD 1/1 3/4 2/2 ADC 1/1 3/4 2/2 SUBC 1/1 3/4 2/2 AND 1/1 3/4 2/2 OR 1/1 3/4 2/2 XOR 1/1 3/4 2/2 IFEQ 1/1 3/4 2/2 IFNE 1/1 3/4 2/2 IFGT 1/1 3/4 2/2 IFBNE 1/1 DRSZ 1/3 SBIT 1/1 3/4 RBIT 1/1 3/4 IFBIT 1/1 3/4 RPND 1/1 Instructions Using A & C CLRA 1/1 INCA 1/1 DECA 1/1 LAID 1/3 DCOR 1/1 RRCA 1/1 RLCA 1/1 SWAPA 1/1 SC 1/1 RC 1/1 IFC 1/1 IFNC 1/1 PUSHA 1/3 POPA 1/3 ANDSZ 2/2 Transfer of Control Instructions JMPL 3/4 JMP 2/3 JP 1/3 JSRL 3/5 JSR 2/5 JID 1/3 VIS 1/5 RET 1/5 RETSK 1/5 RETI 1/5 INTR 1/7 NOP 1/1 Memory Transfer Instructions Register Direct Immed. Register Indirect Indirect Auto Incr. & Decr. [B] [X] [B+, B−] [X+, X−] X A, (Note 14) 1/1 1/3 2/3 1/2 1/3 LD A, (Note 14) 1/1 1/3 2/3 2/2 1/2 1/3 LD B, Imm 1/1 (IF B < 16) LD B, Imm 2/2 (IF B > 15) LD Mem, Imm 2/2 3/3 2/2 LD Reg, Imm 2/3 IFEQ MD, Imm 3/3 Note 14: = > Memory location addressed by B or X or directly. www.national.com 46 |
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