CS5530 datasheet(170/241 Pages) NSC

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Revision 4.1

Index 9Ch-9Dh

Parallel / Serial Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Parallel/SerialIdle Timer Count: This idle timer is used to determine when the parallel and serial ports are not in use

so that the ports can be power managed. The 16-bit value programmed here represents the period of inactivity for these

ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an

access occurs to the parallel (LPT) or serial (COM) I/O address spaces. If the mouse is enabled on a serial port, that port

is not considered here. The counter uses a 1 second timebase.

To enable this timer set F0 Index 81h[2] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[2].

Index 9Eh-9Fh

Keyboard / Mouse Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Keyboard / Mouse Idle Timer Count: This idle timer determines when the keyboard and mouse are not in use so that

the LCD screen can be blanked. The 16-bit value programmed here represents the period of inactivity for these ports

after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an

access occurs to either the keyboard or mouse I/O address spaces, including the mouse serial port address space when

a mouse is enabled on a serial port. The counter uses a 1 second timebase.

To enable this timer set F0 Index 81h[3] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[3].

Index A0h-A1h

User Defined Device 1 Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

User Defined Device 1 (UDEF1) Idle Timer Count: This idle timer determines when the device configured as UDEF1 is

not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this

device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an

access occurs to memory or I/O address space configured in F0 Index C0h (base address register) and F0 Index CCh

(control register). The counter uses a 1 second timebase.

To enable this timer set F0 Index 81h[4] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[4].

Index A2h-A3h

User Defined Device 2 Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

User Defined Device 2 (UDEF2) Idle Timer Count: This idle timer determines when the device configured as UDEF2 is

not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this

device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an

access occurs to memory or I/O address space configured in the F0 Index C4h (base address register) and F0 Index CDh

(control register). The counter uses a 1 second timebase.

To enable this timer set F0 Index 81h[5] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[5].

Index A4h-A5h

User Defined Device 3 Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

User Defined Device 3 (UDEF3) Idle Timer Count: This idle timer determines when the device configured as UDEF3 is

not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this

device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an

access occurs to memory or I/O address space configured in the UDEF3 Base Address Register (F0 Index C8h) and

UDEF3 Control Register (F0 Index CEh). The counter uses a 1 second timebase.

To enable this timer set F0 Index 81h[6] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[6].

Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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