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STA016 Scheda tecnica(PDF) 36 Page - STMicroelectronics |
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STA016 Scheda tecnica(HTML) 36 Page - STMicroelectronics |
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36 / 43 page ![]() STA016A 36/43 Table 39. values to configure system PLL for SYSCK. This table give values to configure the system PLL according CRYCK so that to generate a SYSCK == 50MHz. or SYSCK == 42.5MHz. Table 40. index of the Sampling Frequency. Register CRYCK in MHz 10 CRYCK in MHz 14.31818 CRYCK in MHz 14.7456 PLL_SYSTEM_PEL_50 162 0 28 PLL_SYSTEM_PEH_50 11 0 152 PLL_SYSTEM_NDIV_50 0 0 0 PLL_SYSTEM_XDIV_50 1 1 1 PLL_SYSTEM_MDIV_50 19 13 12 PLL_SYSTEM_PEL_42_5 0 126 100 PLL_SYSTEM_PEH_42_5 0 223 135 PLL_SYSTEM_NDIV_42_5 0 0 0 PLL_SYSTEM_XDIV_42_5 1 1 1 PLL_SYSTEM_MDIV_42_5 16 10 10 Index Frequency 0 48 kHz 1 44.1 kHz 2 32 kHz 4 96 kHz 5 88.2 kHz 6 64 kHz 8 24 kHz 9 22.05 kHz 10 16 kHz 12 12 kHz 13 11.025 kHz 14 8 kHz 16 192 kHz 17 176.4 kHz 18 128 kHz 3, 7, 11, 15 or 19 illegal frequency |
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