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DM54L10J Scheda tecnica(PDF) 1 Page - National Semiconductor (TI) |
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DM54L10J Scheda tecnica(HTML) 1 Page - National Semiconductor (TI) |
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1 / 4 page ![]() TLF6619 June 1989 DM54L10 Triple 3-Input NAND Gates General Description This device contains three independent gates each of which performs the logic NAND function Connection Diagram Dual-In-Line Package TLF6619 – 1 Order Number DM54L10J or DM54L10W See NS Package Number J14A or W14B Function Table Y e ABC Inputs Output AB C Y XX L H XLX H LX X H HHH L H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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