DP83266 datasheet(107/152 Pages) NSC

Il numero della parte	DP83266

Spiegazioni elettronici	MACSITM Device (FDDI Media Access Controller and System Interface)

PDF	152 Pages

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Produttore elettronici	NSC [National Semiconductor (TI)]

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70 Control Information (Continued)

Request Channel 0 and 1 Expected Frame Status Registers (R0EFSR and R1EFSR)

The Expected Frame Status Registers (R0EFSR and R1EFSR) define the matching criteria used for Full Confirmation of

returning frames on each Request Channel A returning frame must meet the programmed criteria to be counted as a matching

returning frame on each Request Channel A returning frame must meet the programmed criteria to be counted as a matching

returning frame

These registers are not altered upon reset

Access Rules

Address

Read

Write

112–113h

Always

VDL

VFCS

EE1

EE0

EA1

EA0

EC1

EC0

Bit

Symbol

Description

D1–D0

EC1–0

Expected C Indicator

EC1

EC0

Value

Any

RorS

D3–D2

EA1–0

Expected A Indicator

EA1

EA0

Value

Any

RorS

D5–D4

EE1–0

Expected E Indicator

EE1

EE0

Value

Any

RorS

VFCS

Valid FCS

When this bit is set returning frames must have a valid FCS field to meet the confirmation

criteria

VDL

Valid Data Length

When this bit is set returning frames must have a valid VDL field to meet the

confirmation criteria

107

DP83266 Scheda tecnica(PDF) 107 Page - National Semiconductor (TI)

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