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DP83256 Scheda tecnica(PDF) 82 Page - Texas Instruments

Il numero della parte DP83256
Spiegazioni elettronici  PLAYER(TM) Device (FDDI Physical Layer Controller)
PDF  146 Pages
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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DP83256 Scheda tecnica(HTML) 82 Page - Texas Instruments

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50 Registers (Continued)
537 SCRUB TIMER VALUE REGISTER (STVR)
This is a snap-shot of the current value of the upper 8 bits of the scrub timer
During a Control Bus Interface write cycle the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register
(ICR) will be set to 1 and will ignore a write cycle
ACCESS RULES
ADDRESS
READ
WRITE
25h
Always
Write Reject
D7
D6
D5
D4
D3
D2
D1
D0
STV7
STV6
STV5
STV4
STV3
STV2
STV1
STV0
Bit
Symbol
Description
D0 – D7
STV0 – STV7
SCRUB TIMER VALUE BITk0-7l
Snap-shot of the scrub timer
STV0 is the Least Significant Bit (LSB)
81



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