1

7

1

1

8

1

1

S

Slave Address

A

DataByte

A

P

MSB

LSB

MSB

LSB

S

StartCondition

Sr

RepeatedStartCondition

1=Read(Rd)FromCDCE9xxDevice;0=Write(Wr)toCDCE9xxx

A

Acknowledge(ACK=0andNACK=1)

P

StopCondition

Master-to-Slave Transmission

Slave-to-Master Transmission

R/W

R/W

1

7

1

1

8

1

1

1

S

Slave Address

Wr

A

A

A

P

DataByte

CommandCode

8

1

7

1

1

1

1

1

1

S

Slave Address

Wr

A

A

S

Rd

A

8

1

1

DataByte

A

P

CommandCode

8

7

Slave Address

1

7

1

1

1

1

S

Slave Address

Wr

A

A

A

8

1

1

1

1

DataByte0

A

A

A

P

8

DataByteN-1

…

8

DataByte1

8

CommandCode

ByteCount=N

8

1

7

1

1

1

1

1

1

S

Slave Address

Wr

A

A

Sr

Rd

A

8

1

1

1

1

ByteCountN

A

A

A

P

DataByte0

…

DataByteN-1

8

CommandCode

7

Slave Address

8

8

CDCE937-Q1

CDCEL937-Q1

www.ti.com

SCAS892B – FEBRUARY 2010 – REVISED MAY 2010

Generic Programming Sequence

Figure 7. Generic Programming Sequence

Byte Write Programming Sequence

Figure 8. Byte Write Protocol

Byte Read Programming Sequence

Figure 9. Byte Read Protocol

Block Write Programming Sequence

(1)

Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose

and should not be overwritten.

Figure 10. Block Write Protocol

Block Read Programming Sequence

Figure 11. Block Read Protocol

Copyright © 2010, Texas Instruments Incorporated

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Product Folder Link(s): CDCE937-Q1