AD6635BBSLASHPCB datasheet(21/60 Pages) AD

Il numero della parte	AD6635BB/PCB

Spiegazioni elettronici	4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)

PDF	60 Pages

Scroll/Zoom	100%

Produttore elettronici	AD [Analog Devices]

Homepage	http://www.analog.com

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AD6635

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TIMING DIAGRAMS – INM Microport Mode (MODE = 0)

CLK0

CLK1

RD (DS)

WR (RW)

CS0

CS1

A[2:0]

D[7:0]

RDY

(

DTACK)

VALID ADDRESS

VALID DATA

NOTES

tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED

FROM FE OF

WR TO RE OF RDY.

tACC REQUIRES A MAXIMUM OF 9 CLK PERIODS.

tSC

tHC

tHWR

tHAM

tSAM

tHAM

tSAM

tDRDY

tACC

Figure 20. INM Microport Write Timing Requirements. CLK0 corresponds to

CS0, and CLK1 to CS1.

CS0 and CS1 both active (low) at the same time will cause errors in writing.

tSC

CLK0

CLK1

RD (DS)

WR (RW)

A[2:0]

D[7:0]

RDY

(

DTACK)

CS0

CS1

NOTES

tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED

FROM FE OF

WR TO RE OF RDY.

tACC REQUIRES A MAXIMUM OF 13 CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 5, 3, 2, 1.

tHC

tSAM

tHAM

VALID ADDRESS

VALID DATA

tDRDY

tACC

Figure 21. INM Microport Read Timing Requirements. CLK0 corresponds to

CS0, and CLK1 to CS1.

CS0 and CS1 both active (low) at the same time will cause contention on data bus.

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