DS90C124IVSSLASHNOPB datasheet(13/31 Pages) TI1

13 / 31 page

DS90C124, DS90C241

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SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013

PIN ASSIGNMENTS

DS90C241 Serializer Pin Descriptions

Pin #

Pin Name

I/O

Description

LVCMOS PARALLEL INTERFACE PINS

4-1,

DIN[23:0]

LVCMOS_I

Transmitter Parallel Interface Data Input Pins. Tie LOW if unused, do not float.

48-44,

41-32,

29-25

TCLK

LVCMOS_I

Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.

CONTROL AND CONFIGURATION PINS

TPWDNB

LVCMOS_I

Transmitter Power Down Bar

TPWDNB = H; Transmitter is Enabled and ON

TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver DOUT (+/-) Outputs are in

TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.

DEN

LVCMOS_I

Transmitter Data Enable

DEN = H; LVDS Driver Outputs are Enabled (ON).

DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver DOUT (+/-) Outputs

are in TRI-STATE, PLL still operational and locked to TCLK.

PRE

LVCMOS_I

Pre-emphasis Level Select

PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).

Pre-emphasis is active when input is tied to VSS through external resistor RPRE. Resistor value

determines pre-emphasis level. Recommended value RPRE ≥ 3 kΩ; Imax = [(1.2/R)*20], Rmin = 3

Ω

TRFB

LVCMOS_I

Transmitter Clock Edge Select Pin

TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge.

TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge

VODSEL

LVCMOS_I

VOD Level Select

VODSEL = L; LVDS Driver Output is

≈±400 mV (RL = 100Ω)

VODSEL = H; LVDS Driver Output is

≈±750 mV (RL = 100Ω)

For normal applications, set this pin LOW. For long cable applications where a larger VOD is

required, set this pin HIGH.

DCAOFF

LVCMOS_I

Reserved. This pin MUST be tied LOW.

DCBOFF

LVCMOS_I

Reserved. This pin MUST be tied LOW.

RESRVD

LVCMOS_I

Reserved. This pin MUST be tied LOW.

LVDS SERIAL INTERFACE PINS

DOUT+

LVDS_O

Transmitter LVDS True (+) Output.

This output is intended to be loaded with a 100

Ω load to the DOUT+ pin. The interconnect should

be AC Coupled to this pin with a 100 nF capacitor.

DOUT

−

LVDS_O

Transmitter LVDS Inverted (-) Output

This output is intended to be loaded with a 100

Ω load to the DOUT-pin. The interconnect should be

AC Coupled to this pin with a 100 nF capacitor.

POWER / GROUND PINS

VDDDR

VDD

Analog Voltage Supply, LVDS Output Power

VSSDR

GND

Analog Ground, LVDS Output Ground

VDDPT0

VDD

Analog Voltage supply, VCO Power

VSSPT0

GND

Analog Ground, VCO Ground

VDDPT1

VDD

Analog Voltage supply, PLL Power

VSSPT1

GND

Analog Ground, PLL Ground

VDDT

VDD

Digital Voltage supply, Tx Serializer Power

VSST

GND

Digital Ground, Tx Serializer Ground

VDDL

VDD

Digital Voltage supply, Tx Logic Power

VSSL

GND

Digital Ground, Tx Logic Ground

VDDIT

VDD

Digital Voltage supply, Tx Input Power

VSSIT

GND

Digital Ground, Tx Input Ground

VSS

GND

ESD Ground

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