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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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DP83902AVF Scheda tecnica(PDF) 45 Page - National Semiconductor (TI) |
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DP83902AVF Scheda tecnica(HTML) 45 Page - National Semiconductor (TI) |
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45 / 70 page  130 Bus Arbitration and Timing (Continued) The FIFO at the Beginning of Transmit Before transmitting the ST-NIC performs a prefetch from memory to load the FIFO The number of bytes prefetched is the programmed FIFO threshold The next BREQ is not issued until after the ST-NIC actually begins transmitting data ie after SFD The Transmit Prefetch diagram illus- trates this process Transmit Prefetch Timing TLF11157 – 59 Maximum Bus Latency for Byte Mode TLF11157 – 60 Maximum Bus Latency for Word Mode TLF11157 – 61 45 |
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