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DP8390DV Scheda tecnica(PDF) 47 Page - National Semiconductor (TI) |
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DP8390DV Scheda tecnica(HTML) 47 Page - National Semiconductor (TI) |
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47 / 56 page ![]() 150 Switching Characteristics (Continued) Wait State Insertion TLF8582 – 45 Symbol Parameter Min Max Units ews External Wait Setup to T3 v Clock 10 ns (Note 1) ewr External Wait Release Time 15 ns (Note 1) Note 1 The addition of wait states affects the count of deserialized bytes and is limited to a number of bus clock cycles depending on the bus clock and network rates The allowable wait states are found in the table below (Assumes 10 Mbitsec data rate) BSCK (MHz) of Wait States Byte Transfer Word Transfer 80 1 10 0 1 12 1 2 14 1 2 16 1 3 18 2 3 20 2 4 Table assumes 10 MHz network clock The number of allowable wait states in byte mode can be calculated using W(byte mode) e 8tnw 45 tbsck b 1 J W e Number of Wait States tnw e Network Clock Period tbsck e BSCK Period The number of allowable wait states in word mode can be calculated using W(word mode) e 5tnw 2 tbsck b 1 J 47 |
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