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DP8392C Scheda tecnica(PDF) 6 Page - National Semiconductor (TI) |
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DP8392C Scheda tecnica(HTML) 6 Page - National Semiconductor (TI) |
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6 / 12 page ![]() 60 Pin Descriptions (Continued) For the PLCC packaged DP8392 it is recommended that a small printed circuit board VEE plane be connected to pins 5 – 11 and a second one be connected to pins 20 – 25 To reduce the thermal resistance to the required value the area of the plane on EACH set of pins should be t020 in2 for applications with low transmitter duty cycle and t04 in2 for high transmit duty cycle applications Figure 7 illustrates a recommended component side layout for these planes TLF11085 – 14 Layout as viewed from component side FIGURE 6 Typical Layout Considerations for DP8392CN (Not to Scale) TLF11085 – 15 FIGURE 7 Recommended Layout and Dissipation Planes for DP8392CV (Not to Scale) 6 |
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