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SLK2501IPZP Scheda tecnica(PDF) 12 Page - Texas Instruments |
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SLK2501IPZP Scheda tecnica(HTML) 12 Page - Texas Instruments |
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12 / 22 page ![]() www.ti.com ABSOLUTE MAXIMUM RATINGS DISSIPATION RATING TABLE RECOMMENDED OPERATING CONDITIONS START UP SEQUENCE SLK2501 SLLS502C – OCTOBER 2001 – REVISED MARCH 2007 over operating free-air temperature range (unless otherwise noted)(1) VALUE UNIT VDD Supply voltage –0.3 to 3 V TTL input terminals –0.3 to 4 V Voltage range LVDS terminals –0.3 to 3 V Any other terminal except above –0.3 to VDD + 0.3 V PD Package power dissipation See Dissipation Rating Table Tstg Storage temperature –65 to 150 °C Electrostatic discharge HBM 2 kV TA Characterized free-air operating temperature range –40 to 85 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. TA≤ 25°C DERATING FACTOR(1) TA = 85°C PACKAGE POWER RATING ABOVE TA = 25¡ãC POWER RATING PZP(2) 3.4 W 33.78 mW/°C 1.3 W PZP(3) 2.27 W 22.78 mW/ °C 0.911 W (1) This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). (2) 2 oz trace and copper pad with solder. (3) 2 oz trace and copper pad without solder. over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 2.3 2.5 2.7 V PD Power dissipation Frequency = 2.488 Gb/sec, PRBS pattern 700 900 mW Shutdown current Enable = 0, Vdda, Vdd pins, Vdd = max 20 µA TA Operating free-air temperature –40 85 °C To ensure proper start up, follow one of the following steps when powering up the SLK2501 device. 1. Keep ENABLE (pin 44) low until power supplies and reference clock have become stable. 2. Drive ENABLE (pin 44) low for at least 30 ns after power supplies and reference clock have become stable. The following step is recommended with either of the above two sequences. 3. Drive RESET low for at least 10 ns after link has become stable to center the TXFIFO. 12 Submit Documentation Feedback |
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