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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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WM8962B Scheda tecnica(PDF) 33 Page - Wolfson Microelectronics plc |
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WM8962B Scheda tecnica(HTML) 33 Page - Wolfson Microelectronics plc |
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33 / 295 page  WM8962 Rev 4.3 33 POWER ON RESET TIMING The WM8962 includes an internal Power-On-Reset (POR) circuit, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DCVDD. The internal POR ¯¯¯ signal is asserted low when AVDD and DCVDD are below minimum thresholds. A secondary reset circuit is associated with the PLLVDD supply. The PLLs are disabled and the associated registers are undefined when PLLVDD is below its minimum threshold. Full device functionality is not possible until AVDD, DCVDD and PLLVDD are above their respective reset thresholds. The WM8962 can operate with PLLVDD tied to 0V, but the crystal oscillator, PLLs and CLKOUT functions will not be supported. The specific behaviour of the circuit will vary, depending on the relative timing of the supply voltages. Typical scenarios are illustrated in Figure 11 and Figure 12. DCVDD 0V 0V AVDD 0V Vpora Vpora_off PLLVDD LO POR Undefined HI Internal POR Internal POR active Internal POR active Device Ready (Full functionality) Vpord_on DCVDD 0V 0V AVDD 0V Vpora Vpora_off PLLVDD LO POR Undefined HI Internal POR Internal POR active Internal POR active Device Ready (excluding PLL functions) Vpord_on Vporp_on Full Functionality Figure 11 Power On Reset Timing - AVDD Enabled First |
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