PC87393 datasheet(89/148 Pages) NSC

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5.0 Game Port (GMP) (Continued)

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5.3.3

Game Port Legacy Status Register (GMPLST)

This register is functional in all Game Port operation modes. Reading this register returns the status and the state of Device

A and B button and Axis pins, as defined in the table below. Writing to the offset of this register initiates a game device po-

sition reading process by forcing a low pulse to be driven on the axis pins in Legacy and Enhanced modes, and by initializing

all position counters in Enhanced mode.

Location:

Offset 01h

Type:

Bit

76543210

Name

Device B

Button 1

Pin Status

Device B

Button 0

Pin Status

Device A

Button 1

Pin Status

Device A

Button 0

Pin Status

Device B

Y-Axis Pin

Status

Device B

X-Axis Pin

Status

Device A

Y-Axis Pin

Status

Device A

X-Axis Pin

Status

Reset

XXXXXXXX

Bit

Description

Device B Button 1 Pin Status. This bit directly reﬂects the status of Device B Button 1 input pin.

0: Low

1: High

Device B Button 0 Pin Status. This bit directly reﬂects the status of Device B Button 0 input pin.

0: Low

1: High

Device A Button 1 Pin Status. This bit directly reﬂects the status of Device A Button 1 input pin.

0: Low

1: High

Device A Button 0 Pin Status. This bit directly reﬂects the status of Device A Button 0 input pin.

0: Low

1: High

Device B Y-Axis Pin Status. This bit reﬂects the state of Device B Y-axis input pin.

0: JOYBY pin is driven low

1: JOYBY pin is released for charging

Device B X-Axis Pin Status. This bit reﬂects the state of Device B X-axis input pin.

0: JOYBX pin is driven lowr

1: JOYBX pin is released for charging

Device A Y-Axis Pin Status. This bit reﬂects the state of Device A Y-axis input pin.

0: JOYAY pin is driven low

1: JOYAY pin is released for charging

Device A X-Axis Pin Status. This bit reﬂects the status of Device A X-axis input pin.

0: JOYAX pin is driven low

1: JOYAX pin is released for charging

PC87393 Scheda tecnica(PDF) 89 Page - National Semiconductor (TI)

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