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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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DP8432V Scheda tecnica(PDF) 19 Page - National Semiconductor (TI) |
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DP8432V Scheda tecnica(HTML) 19 Page - National Semiconductor (TI) |
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19 / 56 page  40 Port A Access Modes (Continued) 453 Delay CAS during Write Accesses Address bit C9 asserted during programming will cause CAS to be delayed until the first positive edge of CLK after RAS is asserted when the input WIN is asserted Delaying CAS during write accesses ensures that the data to be written to DRAM will be setup to CAS asserting as shown in Figures 12a and 12b If the possibility exists that data still may not be present after the first positive edge of CLK CAS can be delayed further with the ECAS inputs If address bit C9 is negated during programming read and write accesses will be treated the same (with regard to CAS) TLF11118 – 18 FIGURE 12a Mode 0 Delay CAS TLF11118 – 19 FIGURE 12b Mode 1 Delay CAS 19 |
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