LM4040C20ILPR datasheet(29/53 Pages) TI1

29 / 53 page

DBZ

(TOP VIEW)

CATHODE

ANODE

Rsup

Vsup

GND

LM4040A10, LM4040A20

www.ti.com

SLOS456M – JANUARY 2005 – REVISED JANUARY 2015

10 Power Supply Recommendations

In order to not exceed the maximum cathode current, be sure that the supply voltage is current limited.

For applications shunting high currents (15 mA max), pay attention to the cathode and anode trace lengths,

adjusting the width of the traces to have the proper current density.

11 Layout

11.1 Layout Guidelines

Figure 10 shows an example of a PCB layout of LM4040XXXDBZ. Some key Vref noise considerations are:

•

Connect a low-ESR, 0.1-

μF (CL) ceramic bypass capacitor on the cathode pin node.

•

Decouple other active devices in the system per the device specifications.

•

Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.

•

Place the external components as close to the device as possible. This configuration prevents parasitic errors

(such as the Seebeck effect) from occurring.

•

Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible and only make perpendicular crossings when absolutely necessary.

11.2 Layout Example

Figure 10. DBZ Layout example

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LM4040C20ILPR Scheda tecnica(PDF) 29 Page - Texas Instruments