TAS3208IPZP datasheet(43/79 Pages) TI1

43 / 79 page

TAS3208

www.ti.com

SLES201E

– JANUARY 2007 – REVISED MARCH 2011

ELECTRICAL SPECIFICATIONS

– ANALOG SECTIONS

(1)

TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, Fs (audio) = 48 kHz, clock source from XTALI, AES17 filter, second-order 30-kHz

low-pass filter (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Stereo MUX Input/ADC Channel

1-kHz sine-wave input

Full-scale input voltage (0 dB)

1.15

Vrms

Input common-mode voltage

Over recommended operating conditions

1.43

1.5

1.57

DNR

–60-dB full-scale input applied at line inputs, A-weighted

dBA

THD + N

1-kHz,

–4-dB full-scale input

–75

–80

PSRR

1 kHz, 100 mVpp on AVDD

Channel separation

1 kHz

–80

–90

Input resistance

14.6

18.33

Input capacitance

DAC Channel/DAC Output

1-kHz sine-wave input, Load = 10 k

Ω, 10 pF

Full-scale output voltage (0 dB)

0.81

0.9

Vrms

Gain error

–10

Output common mode

Over recommended operating conditions

1.43

1.5

1.57

DNR

–60-dB full-scale input applied at line inputs, A-weighted

dBA

THD + N

–1-dBFS input, 0-dB gain

–80

–90

PSRR

1 kHz, 100 mVpp on AVDD, VGND powered down

Load capacitance

Load resistance

Channel separation

–81

–84

1-kHz sine-wave input, Load = 16

Ω,

DAC Channel/ Headphone Output

External series resistance = 16

Ω,

Coupling capacitance = 47

µF

Full-scale output voltage (0 dB)

0.72

0.9

Vrms

DNR

–60-dB full-scale input applied at Line inputs, A-weighted

dBA

THD + N

0-dBFS input, 0-dB gain

–50

–60

PSRR

1 kHz, 100 mVpp on AVDD , VGND powered down

Maximum output power(2)

Load capacitance

100

Load resistance

Channel separation

–70

–80

(1)

When the TAS3208 is operated in slave mode, the internal analog clocks for ADC and DAC are derived from external MCLKIN input. In

this case, the analog performance will depend on MCLKIN quality (i.e., jitter, phase noise, etc.).

(2)

16-

Ω series resistor required in L and R headphone outputs for short-circuit protection.

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