LP3882

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SNVS226F – MARCH 2003 – REVISED APRIL 2013

To understand why a small capacitor can reduce phase margin: assume a typical LDO with a bandwidth of

µF capacitor on the output. This creates a pole whose frequency is:

(3)

This pole would add close to 60 degrees of phase lag at the crossover (unity gain) frequency of 1 MHz, which

would almost certainly make this regulator oscillate. Depending on the load current, output voltage, and

bandwidth, there are usually values of small capacitors which can seriously reduce phase margin. If the

capacitors are ceramic, they tend to oscillate more easily because they have very little internal inductance to

damp it out. If bypass capacitors are used, it is best to place them near the load and use trace inductance to

"decouple" them from the regulator output.

INPUT CAPACITOR

The input capacitor must be at least 4.7 µF, but can be increased without limit. It's purpose is to provide a low

source impedance for the regulator input. Ceramic capacitors work best for this, but Tantalums are also very

good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be

used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application

where temperatures go below about 10°C.

BIAS CAPACITOR

The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended).

BIAS VOLTAGE

The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage

must be in the range of 4.5 - 6V to assure proper operation of the part.

UNDER VOLTAGE LOCKOUT

The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage

is below approximately 4V.

SHUTDOWN OPERATION

Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a

pull-up resistor (10 k

Ω to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high

and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin

if not used.

POWER DISSIPATION/HEATSINKING

A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of

the application. Under all possible conditions, the junction temperature must be within the range specified under

operating conditions. The total power dissipation of the device is given by:

The maximum allowable value for junction to ambient Thermal Resistance,

formula:

These parts are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on amount

of copper area or heat sink, and on air flow. If the maximum allowable value of

for TO-220 package and

≥ 60 °C/W for DDPAK/TO-263 package no heatsink is needed since the package can

dissipate enough heat to satisfy these requirements. If the value for allowable

sink is required.

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