CS5516-AS datasheet(16/41 Pages) CIRRUS

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the proper 24 bit calibration words in the VREF

and AIN non-ratiometric registers. Note that the

two non-ratiometric offsets can be calibrated si-

multaneously or independently, but they must be

calibrated prior to the other calibration steps if

non-ratiometric offset calibration is to be used. If

the effects of the non-ratiometric errors are not

significant enough to affect the user application,

they can be left uncalibrated (after a reset, the

non-ratiometric offset registers will contain

000000(H)).

Ratiometric Offset

Once the non-ratiometric errors have been cali-

brated, the ratiometric offset error of the AIN

channel should be calibrated next. To perform

this calibration step, a reference voltage must be

applied to the VREF+ and VREF- pins. Then,

place "zero" weight on the scale platform. This

will result in an offset voltage into the converter

which will represent the offset of the bridge, the

wiring, and the AIN input of the converter itself.

A configuration word with the EC and CC1 bits

set to logic 1 is then written into the configura-

tion register. During the ratiometric offset

calibration of AIN the microcontroller first uses

a successive approximation algorithm to com-

pute the correct values for the DAC3-DAC0 bits

of the DAC register.

This accommodates any

large offsets on the AIN input signal. Once the

four DAC bits are computed, this amount of off-

set is removed from the input signal. The

microcontroller then computes the appropriate

24 bit number to place in the AIN ratiometric

offset register to calibrate out the remaining off-

set not removed by the DAC.

Gain

After the AIN ratiometric offset has been cali-

brated, the next step is to perform a gain

calibration. Gain calibration is performed with

"full scale" weight on the scale platform. The

EC and CC0 bits of the configuration register

are set to logic 1. The gain calibration of the

AIN channel is the final calibration step. After

DRDY falls to signal the completion of this cali-

bration step, the EC bit of the configuration

the calibration mode.

Limitations in Calibration Range

There are five calibration registers in the con-

verter. There are two non-ratiometric offset

calibration registers, one for the AIN input and

one for the VREF input; one 4-bit offset trim

DAC; one ratiometric offset calibration register

for the AIN input; and one gain calibration reg-

ister. After the non-ratiometric offsets are

calibrated, an LSB in either of the 24-bit non-ra-

tiometric calibration registers represents 2

-23

proportion of an internally-scaled MDRV

(Modulator Differential Reference Voltage). At

the MDRV+ and MDRV- pins, the MDRV has a

nominal value of 3.75 volts. This voltage is in-

ternally scaled to a nominal 2.5 volts (never less

than 2.4 volts) for use with the non-ratiometric

calibration. The two non-ratiometric calibration

words are stored in 2’s complement form with

one count equal to slightly less than 300 nV at

the input of the internal A/D converter. For the

AIN channel this will be scaled down by the

gain of the instrumentation amplifier (X25) and

the PGA gain. For a PGA gain = 1, one count of

a non-ratiometric register will represent slightly

less than 12 nV. Non-ratiometric offset at the

VREF input cannot exceed

± 2.4 volts to be

within calibration range of the converter. Non-

ratiometric offset to be calibrated by the AIN

channel cannot exceed

± 2.4 volts divided by the

channel gain. With a PGA gain = 1, the maxi-

mum non-ratiometric offset which can be

calibrated on the AIN channel cannot exceed

± 96 mV.

When the ratiometric offset is calibrated, the 4-

bit DAC coarsely trims offset from the analog

signal. The ratiometric offset which remains is

finely trimmed after the signal has been con-

verted; using the contents of the ratiometric

offset register for digital correction. The DAC

CS5516, CS5520

DS74F1

DS74F2

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