MCP2050-ESLASHP datasheet(5/40 Pages) MICROCHIP

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DS20002299C-page 5

MCP2050

1.2

Windowed Watchdog Reset

The Watchdog Timer monitors for activity on the

Windowed

Watchdog

Timer

Trigger

input

WWDTTRIG. The WWDTTRIG pin is expected to be

strobed within a given time frame. When this time frame

has expired without an edge transition on the WWDTTRIG

pin, the WWDTRESET pin is driven active (low) to reset

the system. This feature is enabled by connecting a

resistor between the WWDTSELECT pin and VSS.

Monitoring is then done by requiring the host processor to

force a falling edge transition on the WWDTTRIG pin

within a predetermined time frame (TWD).

The start time of the trigger window is fixed at 50% of

the total watchdog period, after the last trigger. The

length of the window is determined by the value of the

resistor on pin WWDTSELECT. The Watchdog Timer is

disabled if WWDTSELECT is floating.

1.2.1

WWDT DURING INITIAL POWER-UP

The WWDTRESET is driven high after a power-on

reset. The Watchdog Timer begins counting at this

point, awaiting an edge on WWDTTRIG pin. Note that

there is no window enabled, yet. If no falling edge is

detected on the WWDTTRIG pin before the timer

expires, the WWDTRESET is pulse low and the timer

is restarted. When a trigger edge on the WWDTTRIG

pin is seen, the window is enabled and the timer is reset.

FIGURE 1-2:

WWDTRESET DURING INITIAL POWER-UP

Figure 1-2 shows the behavior of the WWDTRESET

pin after a system reset with no trig at all. If no trig is

given during the power-up window, WWDTRESET is

reset low for the time tWDRST.

The power-up window length tPOWERUP duration is

determined by the value of the resistor connected

between pin WWDTSELECT and pin VSS, while the

reset pulse duration is about 150 μs.

Duration for tPOWERUP and tWDRST are:

•tPOWERUP = 0.8 ms x (RWWDTSELECT+1) typical

•tWDRST = 150 μs typical

•RWWDTSELECT is in kΩ



Once a trig is asserted, the power-up sequence “stops”

and the normal behavior begins.

TABLE 1-1:

OVERVIEW OF OPERATIONAL MODES

State

Transmitter Receiver

Internal

Wake Module

Voltage

Regulator

Watch Dog

Timer

Operation

Comments

PoR

Off

Proceed to Ready mode after VBB>VON.—

Ready

Off

If CS/LWAKE high, then proceed to Operation

or Transmitter Off mode.

Bus Off state

Operation

Off

If CS/LWAKE low level, then proceed to

Power-Down.

If FAULT/TXE low level, then Transmitter-Off

mode.

Normal

Operation

mode

Power-Down

Off

Activity Detect

Off

On LIN bus rising edge or CS/LWAKE high

level, proceed to READY mode.

Lowest-

Power mode

Transmitter Off

Off

If CS/LWAKE low level, then proceed to

Power down.

If FAULT/TXE high, then Operation mode.

Bus Off state,

Lower-Power

mode

tPOWERUP

tWDRST

tPOWERUP

Internal

reset

WWDTRESET

tPOWERUP

tWDRST

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